| Job Title | Principal Design Engineer |
|---|---|
| Category | Engineering |
| Location | Indore |
| Company | Cadence |
| Description | Requirements: · Education: o College education in Electronics Engineering or Computer Engineering · Experience/Abilities: o Candidate should be proficient in ASIC development flows like RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT, lint, CDC, LEC etc. o Familiarity with Power Flow (UPF/CPF). o Experience with functional simulation using Verilog/System Verilog and ability to debug existing Verilog/System Verilog test cases with little or no help from the designer o Good in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging. Checks and validation of package consistency. o Bug reporting and resolution closure with IP providers o Ability to debug synthesis/timing analysis constraints, reports, logs o Ability to learn new tools/flows and develop methodology if needed. o 8+ years of relevant experience in Digital Design and verification. · Soft Skills: o Ability to build and maintain close relationships with all stake holders such as RnD, Application/Product Engineers, Program Managers, Sales, etc o Strong communication skills, both oral and written o Need to be results and data driven while being able to pay attention to details o Good time management skills to balance multiple high-priority projects. o Ability to efficiently lead and train teams o Fastidious approach to building automated processes. o Strong interpersonal and relationship-building skills. o Passionate about quality and ensuring our customer have the best experience · Additional Desirable Qualifications: o Familiarity with HBM/DDR Design-IP’s & Analog design flows |
| Salary | As per organization norms |
| Last Date | 2026-02-23 00:00:00 |
| Apply Link | Click Here |
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